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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 1 1 publication order number: ncp81252/d ncp81252 single-phase voltage regulator with svid interface for computing applications high switching frequency, high efficiency, integrated power mosfets the ncp81252, a single?phase synchronous buck regulator, integrates power mosfets to provide a high?efficiency and compact?footprint power management solution for new generation computing cpus. the device is able to deliver up to 14 a tdc output current on an adjustable output with svid interface. operating in high switching frequency up to 1.2 mhz allows employing small size inductors and capacitors while maintaining high efficiency due to integrated solution with high performance power mosfets. current?mode rpm control with feedforward from both input power supply and output voltage ensure s stable operation over wide operation condition. the ncp81252 is in a qfn48 6 x 6 mm package. features ? meets intel ? server specifications ? 5 v to 20 v input voltage range ? 0.9 v/1.35 v fixed boot voltage ? adjustable output voltage with svid interface ? integrated gate driver and power mosfets ? up to 14 a tdc output current ? 500 khz ~ 1.2 mhz switching frequency ? current?mode rpm control ? programmable svid address and iccmax ? adaptive voltage positioning (avp) ? programmable dvid feed?forward to support fast dvid ? feedforward operation for input supply voltage and output voltage ? output over?voltage and under?voltage protections ? external current limitation programming with inductor current sense ? qfn48, 6 x 6 mm, 0.4 mm pitch package ? this is a pb?free device typical applications ? server applications device package shipping ? ordering information NCP81252MNTXG qfn48 (pb?free) 2500 / tape & reel qfn48 case 485cj marking diagram www. onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 48 1 ncp81252 awlyywwg 1 ncp81252 = specific device code a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package
ncp81252 www. onsemi.com 2 vin 50 vrhot# 47 46 en 48 sdio 2 alert# 3 sclk 4 gnd 5 vrrdy 6 7 8 9 10 11 12 vcc vsp 44 43 vsn 45 diffout fb 41 40 comp 42 freq csref 38 37 cssum 39 cscomp ilim 14 15 13 17 18 16 20 21 19 23 24 22 iout 36 imax 35 gnd 34 tsense 33 vccp 32 sw 31 30 29 28 27 26 25 sw vin sw vin bst gh sw vin vin vin sw sw pgnd pgnd pgnd pgnd vin vin sw pgnd vin pgnd sw 51 gnd 49 vboot gl 1 figure 1. pin configuration (top view) sw vin sw bst vccp ilim gnd freq vcc en vrhot# pgnd sdio alert# sclk imax tsense csref cssum cscomp vsn fb vrrdy vin +5v vout ncp81252 vsp diffout iout comp gl vboot gh figure 2. typical application circuit
ncp81252 www. onsemi.com 3 pwm control svid interface uvlo vin sw pgnd en fb vcc gnd bst gh gl iout ilim csc omp comp diff out vsp vsn freq imax sclk ale rt# sdio vrh ot# vccp gate drive vccp error amp thermal management differential amplifier csr ef css um current sense vrrd y control logic & protections & vr ready vin vsp?vsn tsense vboot iout imax mux adc registers dac dac dac vref vref current measurement and limit frequency & vboot detection vin dac comp ocp vsp?vsn dac v cs pwm dvid feedforward tsen se imon ocp tsense vbo ot 1.3v cscomp csref figure 3. functional block diagram 0.5 vdroop
ncp81252 www. onsemi.com 4 table 1. pin description pin name type description 1 vrhot# logic output vr hot. logic low output represents over temperature. 2 sdio logic bidirectional serial data io port. data port of svid interface. 3 alert# logic output alert. open?drain output. provides a logic low valid alert signal of svid interface. 4 sclk logic input serial clock. clock input of svid interface. 5, 32, 49 gnd analog ground analog ground. ground of internal control circuits. must be connected to the system ground. 6 vrrdy logic output voltage regulator ready. open?drain output. provides a logic high valid power good output signal, indicating the regulator?s output is in regulation window. 7, 11?17, 50 vin power input power supply input. these pins are the power supply input pins of the device, which are connected to drain of internal high?side power mosfet. 22 f or more ceramic capacitors must bypass this input to power ground. the capacitors should be placed as close as possible to these pins. 8 bst power bidirectional bootstrap. provides bootstrap voltage for the high?side gate driver. a 0.1 f ~ 1 f ceramic capacitor is required from this pin to sw (pin10). a 1 ~ 2 resistor may be employed in series with the bst cap to reduce switching noise and ringing when needed. 9 gh analog output gate of high?side mosfet. directly connected with the gate of the high?side power mosfet. 10 sw power return switching node. provides a return path for integrated high?side gate driver. it is internally connected to source of high?side mosfet. 18, 25?29, 51 sw power output switch node. pins to be connected to an external inductor. these pins are interconnection between internal high?side mosfet and low?side mosfet. 19?24 pgnd power ground power ground. these pins are the power supply ground pins of the device, which are connected to source of internal low?side power mosfet. must be connected to the system ground. 30 gl analog output gate of low?side mosfet. directly connected with the gate of the low?side power mosfet. 31 vboot analog input boot?up voltage. a resistor from this pin to ground programs svid address. 33 vccp analog power voltage supply of gate driver. power supply input pin of internal gate driver. a 4.7 f or larger ceramic capacitor bypasses this input to ground. this capacitor should be placed as close as possible to this pin. 34 tsense analog temperature sense. an external temperature sense network is connected to this pin. 35 imax analog input current maximum. a resistor from this pin to ground programs imax. 36 iout analog output out current monitor. provides output signal representing output current by connecting a resistor from this pin to ground. shorting this pin to ground disables imon function. 37 ilim analog output limit of current. a resistor from this pin to cscomp programs over?current threshold with inductor current sense. 38 cscomp analog output current sense comp. output pin of current sense amplifier. 39 cssum analog input current sense sum. inverting input of current sense amplifier. 40 csref analog input current sense reference. non?inverting input of current sense amplifier. 41 freq analog input frequency. a resistor from this pin to ground programs switching frequency. 42 comp analog compensation. output pin of error amplifier. 43 fb analog input feedback. inverting input to error amplifier. 44 diffout analog output differential amplifier output. output pin of differential voltage sense amplifier. 45 vsn analog input voltage sense negative input. inverting input of differential voltage sense amplifier. it is also used for dvid feed forward function with an external resistor. 46 vsp analog input voltage sense positive input. non?inverting input of differential voltage sense amplifier. 47 vcc analog power voltage supply of controller. power supply input pin of control circuits. a 1 f or larger ceramic capacitor bypasses this input to ground. this capacitor should be placed as close as possible to this pin. 48 en logic input enable. logic high enables the device and logic low makes the device in standby mode.
ncp81252 www. onsemi.com 5 table 2. maximum ratings rating symbol value unit min max power supply voltage to pgnd v vin 30 v switch node to pgnd v sw 30 v analog supply voltage to gnd v cc, v ccp ?0.3 6.5 v bst to pgnd bst_pgnd ?0.3 33 38 (<50 ns) v bst to sw bst_sw ?0.3 6.5 v gh to sw gh ?0.3 ?2 (<200 ns) bst+0.3 v gl to gnd gl ?0.3 ?2 (<200 ns) vccp+0.3 v vsn to gnd vsn ?0.3 0.3 v iout iout ?0.3 2.5 v pgnd to gnd pgnd ?0.3 0.3 v other pins ?0.3 vcc+0.3 v latch up current: (note 1) all pins, except digital pins digital pins i lu ?100 ?10 100 10 ma operating junction temperature range t j ?40 125 c operating ambient temperature range t a ?40 125 c storage temperature range t stg ?40 150 c thermal resistance junction to board (note 2) r jb 8.2 c/w thermal resistance junction to ambient (note 2) r ja 21.8 c/w power dissipation at t a = 25 c (note 3) p d 4.59 w moisture sensitivity level (note 4) msl 3 ? stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. latch up current per jedec standard: jesd78 class ii. 2. the thermal resistance values are dependent of the internal losses split between devices and the pcb heat dissipation. this d ata is based on a typical operation condition with a 4?layer fr?4 pcb board, which has two, 1?ounce copper internal power and ground planes and 2?ounce copper traces on top and bottom layers with approximately 80% copper coverage. no airflow and no heat sink applied (ref erence eia/jedec 51.7). it also does not account for other heat sources that may be present on the pcb next to the device in question (such as inductors, resistors etc.) 3. the maximum power dissipation (pd) is dependent on input voltage, output voltage, output current, external components selecte d, and pcb layout. the reference data is obtained based on t jmax = 125 c and r ja = 21.8 c/w. 4. moisture sensitivity level (msl): 3 per ipc/jedec standard: j?std?020d.1.
ncp81252 www. onsemi.com 6 table 3. electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, v out = 1.0 v, typical values are referenced to t j = 25 c, min and max values are referenced to t j from ?40 c to 125 c. unless otherwise noted.) characteristics test conditions symbol min typ max unit supply voltage supply voltage v in range (note 5) v in 12 v supply voltage v cc range (note 5) v cc 4.75 5 5.25 v supply voltage v ccp range (note 5) v ccp 4.75 5 5.25 v supply voltage monitor v in uvlo falling threshold v inuv? 3.0 3.25 3.5 v hysteresis v inhys 650 ? mv v cc uvlo falling threshold v ccuv? 3.8 4.08 ? v rising threshold v ccuv+ ? 4.34 4.5 v hysteresis v cchys ? 260 ? mv supply current v in quiescent supply current (power mosfets) en high, no load, ps0,1,2 modes en high, no load, ps3 mode en high, ps4 mode (note 6) i q ? ? ? 1.5 1.5 ? 3 3 1 ma ma a v in shutdown current en low (note 6) i sd ? ? 1 a v cc quiescent supply current (controller) en high, no load, ps0,1,2 modes en high, no load, ps3 mode en high, ps4 mode (note 6) i qcc ? ? ? 8.0 7.5 170 12 12 194 ma ma a v cc shutdown current en low (note 6) i sdcc ? ? 100 a v ccp quiescent supply current (gate driver) en high, no load, ps0,1,2 modes en high, no load, ps3 mode en high, ps4 mode i qccp ? ? ? 0.7 0.7 ? 1.25 1.25 2 ma ma a v ccp shutdown current en low i sdccp ? ? 2 a output voltage output voltage range (note 5) v out 0 ? 2.3 v regulation accuracy system voltage accuracy 0.25 v < dac < 0.8 v 0.8 v < dac < 1.0 v 1.0 v < dac < 1.52 v ?8 ?10 ?0.9 +8 +10 +0.9 mv mv % dvid fast slew rate default fsr 14 mv/ s soft start slew rate sssr fsr/4 mv/ s slow slew rate ssr fsr/2 fsr/4 (default) fsr/8 fsr/16 mv/ s differential voltage?sense amplifier dc gain vsp?vsn = 0.5 v to 2.3 v gain_dva 1.0 v/v ?3 db gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd (note 5) bw_dva 10 mhz vsp input voltage range (note 5) vsp ?0.3 ? 3.0 v vsn input voltage range (note 5) vsn ?0.3 ? 0.3 v input bias current vsp,csref = 1.3 v i vsp i vsn ?15 ?100 15 100 a na 5. guaranteed by design, not tested in production. 6. t j = 25 c.
ncp81252 www. onsemi.com 7 table 3. electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, v out = 1.0 v, typical values are referenced to t j = 25 c, min and max values are referenced to t j from ?40 c to 125 c. unless otherwise noted.) characteristics unit max typ min symbol test conditions differential current?sense amplifier dc gain (note 5) gain_dca 80 db ?3db gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd (note 5) bw_dca 10 mhz input offset voltage v os_cs ?300 ? 300 v input bias current cssum = csref = 1.2 v i cssum i csref ?7.5 ?10 7.5 10 na a error amplifier dc gain cl = 20 pf to gnd, rl = 10 k to gnd (note 5) gain_ea 80 db unity gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd (note 5) bw_ea 20 mhz slew rate vin = 100 mv, g = ?10 v/v, vout = 1.5 v ? 2.5 v, cl = 20 pf to gnd, rl = 10 k to gnd (note 5) sr_ea 25 v/ s output voltage swing isource_ea = 2 ma vmax_ea 3.5 ? ? v isink_ea = 2 ma vmin_ea ? ? 1 fb voltage v fb 1.3 v input bias current vfb = 1.3 v i fb ?1.5 1.5 a switching frequency normal operation frequency (programmed by a resistor at freq pin) (note 5) fsw 500 1200 khz freq output voltage vfreq 1.95 2.0 2.05 v control logic enable input high voltage ven_h 0.8 ? ? v enable input low voltage ven_l ? ? 0.3 v enable input hysteresis ven_hys ? 300 ? mv enable input bias current ien_bias ? 1.0 a tsense alert# assert threshold 491 mv alert# de?assert threshold 513 mv vr_hot# assert threshold 472 mv vr_hot# de?assert threshold 494 mv tsense bias current v tsense = 0.4 v 112 120 128 a vboot sensing current v vboot = gnd 10 a imax sensing current v imax = gnd 10 a 5. guaranteed by design, not tested in production. 6. t j = 25 c.
ncp81252 www. onsemi.com 8 table 3. electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, v out = 1.0 v, typical values are referenced to t j = 25 c, min and max values are referenced to t j from ?40 c to 125 c. unless otherwise noted.) characteristics unit max typ min symbol test conditions adc voltage range 0 2.0 v total unadjusted error (tue) ?1 1 % differential nonlinearity (dnl) 8?bit 1 lsb power supply sensitivity 1 % conversion time 30 s round robin 90 s vr_ready (vrrdy output) rise time external 1 k pull?up to 3.3 v, ctot = 45 pf, vo = 10% to 90% 120 ns fall time external 1 k pull?up to 3.3 v, ctot = 45 pf, vo = 90% to 10% 20 ns output voltage at power?up pulled up to 5 v via 2 k ? ? 1.0 v vr_ready delay (rising) dac = target to vr_ready 50 s vr_ready delay (falling) from ocp or ovp 5 s vrrdy pin low voltage voltage at vrrdy pin with 4 ma sink current vpg_l ? ? 0.3 v vrrdy pin leakage current vrrdy = 5 v pg_lk ?1.0 ? 1.0 a over voltage protection absolute over voltage threshold during soft?start 2.8 2.9 3.0 v over voltage threshold above dac vsp rising 350 400 425 mv over voltage delay vsp rising to gh low 50 ns under voltage protection under voltage threshold below dac vsp falling 250 300 350 mv under?voltage delay 5 s over current protection ilim threshold current (ocp shutdown after 50 s delay) i limth_slow 8.5 10.0 12.0 a ilim threshold current (immediate ocp shutdown) i limth_fast 12.0 15.0 18.0 a iout output current gain (ioutcurrent) / (ilimcurrent); rilim = 20 k ; riout = 5.0 k ; dac = 0.8 v, 1.25 v, 1.52 v 9.5 10 10.5 a/a input referred offset voltage ilim ? csref ?5.5 ? 5.5 mv output source current ilim sink current = 80 a 800 a high?side mosfet drain?to?source on resistance v gs = 4.5 v, i d = 10 a r on_h ? 8.0 ? m low?side mosfet drain?to?source on resistance v gs = 4.5 v, i d = 10 a r on_l ? 4.0 ? m 5. guaranteed by design, not tested in production. 6. t j = 25 c.
ncp81252 www. onsemi.com 9 table 3. electrical characteristics (v in = 12 v, v cc = v ccp = 5 v, v out = 1.0 v, typical values are referenced to t j = 25 c, min and max values are referenced to t j from ?40 c to 125 c. unless otherwise noted.) characteristics unit max typ min symbol test conditions high?side gate drive pull?high drive on resistance v bst ? v sw = 5 v r drv_hh ? 1.2 2.9 pull?low drive on resistance v bst ? v sw = 5 v r drv_hl ? 0.8 2.2 gh propagation delay time from gl falling to gh rising t gh_d 15 ns low?side gate drive pull?high drive on resistance v ccp ? v pgnd = 5 v r drv_lh ? 0.9 3.0 pull?low drive on resistance v ccp ? v pgnd = 5 v r drv_ll ? 0.4 1.25 gl propagation delay time from gh falling to gl rising t gl_d 10 ns sw to pgnd resistance sw to pgnd pull?down resistance (note 5) r sw ? 1.88 ? k bootstrap rectifier switch on resistance en = l or en = h and drvl = h r on_bst 5 13 22 5. guaranteed by design, not tested in production. 6. t j = 25 c. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp81252 www. onsemi.com 10 v th v th 1.0 v t gh_d t gl_d t gh_r t gh_f t gl_r gl gh to sw sw t gl_f note: timing is referenced to the 90% and 10% points, unless otherwise noted. figure 4. timing diagram of gate drivers table 4. state truth table state vr_rdy pin error amp comp pin ovp & uvp method of reset por 0 < vcc < uvlo n/a n/a n/a disabled en < threshold uvlo > threshold low low disabled start up delay & calibration en > threshold uvlo > threshold low low disabled soft start en > threshold uvlo > threshold low operational active / no latch normal operation en > threshold uvlo > threshold high operational active / latching n/a over voltage low n/a dac + 400 mv over current low operational last dac code vout = 0 v low: if reg34h:bit0 = 0; high:if reg34h:bit0 = 1 clamped at 0.9 v disabled
ncp81252 www. onsemi.com 11 detailed description general the ncp81252, a single?phase synchronous buck regulator, integrates power mosfets to provide a high?ef ficiency and compact?footprint power management solution for new generation computing cpus. the device is able to deliver up to 14 a tdc output current on an adjustable output with svid interface. operating in high switching frequency up to 1.2 mhz allows employing small size inductors and capacitors while maintaining high efficiency due to integrated solution with high performance power mosfets. current?mode rpm control with feedforward from both input power supply and output voltage ensures stable operation over wide operation condition. current?mode rpm operation the ncp81252 operates with the current?mode ramp?pulse?modulation (rpm) scheme in ps0/1/2/3 operation modes. in forced ccm mode, the inductor current is always continuous and the device operates in quasi?fixed switching frequency, which has a typical value programmed by users through a resistor at pin freq. in auto ccm/dcm mode, the inductor current is continuous and the device operates in quasi?fixed switching frequency in medium and heavy load range, while the inductor current becomes discontinuous and the device automatically operates in pfm mode with an adaptive fixed on time and variable switching frequency in light load range. serial vid interface (svid) the ncp81252 supports intel serial vid interface. it communicates with the microprocessor through three wires (sclk, sdio, alert#). for ncp81252, vid code change rate is controlled by the svid interface with three options. information regarding svid interface can be obtained from intel. boot voltage and svid address table 5 shows two boot voltage options of 0.9 v and 1.35 v programmed by an external 1% resistor rvboot from vboot pin to gnd, which programs svid address as well. both values are set on power up and cannot be changed after the initial power up sequence is complete. table 5. boot voltage and svid address configuration rvboot ( ) vboot pin voltage (mv) address vboot (v) min typ max 0 0 0 102 0x0 0.9 14 .0k 102 140 180 0x1 0.9 22.1 k 180 219 258 0x2 0.9 30.1 k 258 301 344 0x3 0.9 39.2 k 344 391 438 0x4 0.9 48.7 k 438 484 531 0x5 0.9 57.6 k 531 578 625 0x6 0.9 68.1 k 625 676 727 0x7 0.9 78.7 k 727 781 836 0x8 0.9 88.7 k 836 894 953 0x0 1.35 100 k 953 1007 1062 0x1 1.35 113 k 1062 1125 1188 0x2 1.35 124 k 1188 1250 1312 0x3 1.35 137 k 1312 1378 1445 0x4 1.35 150 k 1445 1511 1578 0x5 1.35 165 k 1578 1648 1719 0x6 1.35 178 k 1719 1789 1859 0x7 1.35 196 k 1859 1950 ? 0x8 1.35
ncp81252 www. onsemi.com 12 switching frequency switching frequency is programmed by a resistor r freq to ground at the freq pin. the typical frequency range is from 500 khz to 1.2 mhz. the freq pin provides approximately 2 v out and the source current is mirrored into the internal ramp generator. the switching frequency can be found in figure 5 with a given r freq . the frequency shown in figure 5 is under condition of 10 a output current at vid = 1 v. the frequency has a variation over vid voltage and loading current, which maintains similar output ripple voltage over different operation condition. figure 6 shows frequency variations over the vid voltage range. figure 5. switching frequency vs. r freq figure 6. switching frequency vs. vid voltage
ncp81252 www. onsemi.com 13 remote voltage sense a high performance differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the output (difout) of the remote sense amplifier is a sum of the error voltage (between the output vsp?vsn and the dac), a load?line voltage vdroop, and a 1.3 v dc bias. v difout v vsp v vsn 1.3 v v dac v_droop (eq. 1) the vdroop voltage is a half of the voltage difference between the cscomp pin and the csref pin. v droop 0.5 v cs 0.5 v csref v cscomp (eq. 2) the difout signal then goes through a compensation network and into the inverting input (fb pin) of an error amplifier. the non?inverting input of the error amplifier is connected to the same 1.3 v used for the differential sense amplifier output bias. current sense cscomp csref cssum 38 39 40 l dcr ccs1 rcs2 rcs3 sw vout vcs rcs1 ccs2 rcs_ntc i out 0.5 v droop ilim 37 r ilim iccmax & iout & ilim iout 36 r iout iccmax 35 r iccmax figure 7. differential current?sense circuit diagram differential current sense the differential current?sense circuit diagram is shown in figure 7. an internally?used voltage signal vcs, representing the inductor current level, is the voltage difference between csref and cscomp. the output side of the inductor is used to create a low impedance virtual ground. the current?sense amplifier actively filters and gains up the voltage applied across the inductor to recover the voltage drop across the inductor?s dc resistance (dcr). rcs_ntc is placed close to the inductor to sense the temperature. this allows the filter time constant and gain to be a function of the rth_ntc resistor and compensate for the change in the dcr with temperature. the dc gain in the current sensing loop is g cs v cs v dcr v csref v cscomp i out dcr r cs r cs3 (eq. 3) where r cs r cs2 r cs1 r cs_ntc r cs1 r cs_ntc (eq. 4) the values of rcs1 and rcs2 are set based on a 220k ntc thermistor and the temperature effect of the inductor and thus usually they should not need to be changed. the gain gcs can be adjusted by the value change of the rcs3 resistor. the internal vcs voltage should be set to the output voltage droop in applications with a dc load line requirement. in order to recover the inductor dcr voltage drop current signal, the pole frequency in the cscomp filter should be set equal to the zero from the output inductor, that means c cs1 c cs2 l dcr r cs (eq. 5) ccs1 and ccs2 are in parallel to allow for a fine tuning of the time constant using commonly available values. in applications with a droop voltage v droop , the dc load line ll can be obtained by ll v droop i out 0.5 v csref v cscomp i out (eq. 6) 0.5 r cs r cs3 dcr
ncp81252 www. onsemi.com 14 over current protection the ncp81252 provides two different types of current limit protection. current limits are programmed with a resistor rilim between the cscomp pin and the ilim pin. the current from the ilim pin to this resistor is then compared to two internal currents (10 a and 15 a) corresponding to two dif ferent current limit thresholds ilim and ilim_fast (150% of ilim level). if the ilim pin current exceeds the 10 a level, an internal latch?off timer starts. the controller shuts down if the fault is not removed after 50 s. if the current into the pin exceeds 15 a the controller will shut down immediately. to recover from an ocp fault the en pin must be cycled low. the value of rilim can be designed using the following equation with a required over current protection threshold ilim and a known current?sense network. r ilim v cs @i lim 10 r cs r cs3 i lim_pk dcr 10 5 (eq. 7) r cs r cs3 i lim v in v out v out 2 l f sw v in dcr 10 5 icc_max a resistor connected from imax pin to ground sets icc_max value at startup. a 10 a current is sourced from this pin to generate a voltage on the program resistor. the resistor value can be determined by the following equation. the resistor value should be no less than 10 k. icc_max r iccmax 10 64 2 r iccmax 3.2 10 ?4 (eq. 8) iout the iout pin sources a current equal to the ilim sink current gained by the iout current gain (10 typ.). the voltage of the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull?up resistor to 5 v v cc can be used to offset the iout signal positive if needed. r iout 2 10 v cs @icc_max r ilim (eq. 9) 1 5 r cs r cs3 icc_max dcr r ilim input uvlo protection ncp81252 monitors supply voltages at the vcc pin and the vin pins in order to provide under voltage protection. if either supply drops below its threshold, the controller will shut down the outputs. upon recovery of the supplies, the controller reenters its startup sequence, and soft start begins. output under?voltage protection the output voltage is monitored by a dedicated differential amplifier. if the output falls below target by more than ?under voltage threshold below dac?droop?, the uvl comparator sends the vr_rdy signal low. output over?voltage protection during normal operation the output voltage is monitored at the differ ential inputs vsp and vsn. if the output voltage exceeds the dac voltage by ?over v oltage threshold above dac?, gh will be forced low, and gl will go high. after the ovp trips, the dac ramps slowly down to zero to avoid a negative output voltage spike during shutdown. if the dac+ovp threshold drops below the output, gl will again go high, and will toggle between low and high as the output voltage follows the dac+ovp threshold down. when the dac gets to zero, the gh will be held low and the gl will remain high. to reset the part, the en pin must be cycled low. during soft?start, the ovp threshold is set to 2.9 v. this allows the controller to start up without false triggering the ovp. (a) normal operation mode (b) during start up figure 8. function of over voltage protection
ncp81252 www. onsemi.com 15 temperature sense and thermal alert the ncp81252 provides an external temperature sense and a thermal alert in normal operation mode. the temperature sense and thermal alert circuit diagram is shown in figure 9. a precision current i tsense is sourced out the output of the tsense pin to generate a voltage across the temperature sense network, which consists of a ntc thermistor r_ntc (100 k typ.), two resistors r_comp1 (0 typ.) and r_comp2 (8.2 k typ.), and a filter capacitor c_filter (0.1 f typ.). the voltage on the temperature sense input is sampled by the internal a/d converter and then digitally converted to temperature and stored in svid register 17h. usually the thermistor is placed close to a hot spot like inductor or ncp81252 itself. a 100k ntc thermistor similar to the murata ncp15wf104d03rc should be used. the ncp81252 also monitors the voltage at the tsense pin and compares the voltage to internal thresholds and assert alert# or vrhot# once it trips the thresholds. the dc voltage at tsense pin can be calculated by v tsense i tsense r comp1 r comp2 r ntc_t r comp2 r ntc_t (eq. 10) r ntc_t is the resistance of r_ntc at an absolute temperature t, which is obtained by r ntc_t r ntc_t 0 exp b 1 t 1 t 0 (eq. 11) where r ntc_t0 is a known resistance of r_ntc at an absolute temperature t 0 , and b is the b?constant of r_ntc. 34 tsense 3 alert# r_ntc r_comp1 3.3v alert# thermal management r_comp2 c_filter 1 vrhot# vrhot# figure 9. temperature sense and thermal alert circuit diagram
ncp81252 www. onsemi.com 16 layout guidelines electrical layout considerations good electrical layout is a key to make sure proper operation, high efficiency, and noise reduction. electrical layout guidelines are: ? power paths: use wide and short traces for power paths (such as vin, vout, sw, and pgnd) to reduce parasitic inductance and high?frequency loop area. it is also good for efficiency improvement. ? power supply decoupling: the device should be well decoupled by input capacitors and input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. usually, a small low?esl mlcc is placed very close to vin and pgnd pins. ? vcc decoupling: place decoupling caps as close as possible to the controller vcc and vccp pins. the filter resistor at vcc pin should be not higher than 2.2 to prevent large voltage drop. ? switching node: sw node should be a copper pour, but compact because it is also a noise source. ? bootstrap: the bootstrap cap and an option resistor need to be very close and directly connected between pin 8 (bst) and pin 10 (sw). no need to externally connect pin 10 to sw node because it has been internally connected to other sw pins. ? ground: it would be good to have separated ground planes for pgnd and gnd and connect the two planes at one point. directly connect gnd pin to the exposed pad and then connect to gnd ground plane through vias. ? voltage sense: use kelvin sense pair and arrange a ?quiet? path for the differential output voltage sense. ? current sense: careful layout for current sensing is critical for jitter minimization, accurate current limiting, and iout reporting. the filter cap from cscomp to csref should be close to the controller. the temperature compensating thermistor should be placed as close as possible to the inductor. the wiring path should be kept as short as possible and well away from the switch node. ? compensation network: the small feedback cap from comp to fb should be as close to the controller as possible. keep the fb traces short to minimize their capacitance to ground. ? svid bus: the serial vid bus is a high speed data bus and the bus routing should be done to limit noise coupling from the switching node. the signals should be routed with the alert# line in between the svid clock and svid data lines. the svid lines must be ground referenced and each line?s width and spacing should be such that they have nominal 50 impedance with the board stackup. thermal layout considerations good thermal layout helps high power dissipation from a small package with reduced temperature rise. thermal layout guidelines are: ? the exposed pads must be well soldered on the board. ? a four or more layers pcb board with solid ground planes is preferred for better heat dissipation. ? more free vias are welcome to be around ic and underneath the exposed pads to connect the inner ground layers to reduce thermal impedance. ? use large area copper pour to help thermal conduction and radiation. ? do not put the inductor to be too close to the ic, thus the heat sources are distributed.
ncp81252 www. onsemi.com 17 package dimensions qfn48 6x6, 0.4p case 485cj issue a seating note 4 0.15 c (a3) a a1 d2 b 1 13 25 48 2x 2x e3 48x l bottom view detail a top view side view d a b e 0.15 c pin one reference 0.10 c 0.08 c c 37 e a 0.10 b c 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip 4. coplanarity applies to the exposed pad as well as the terminals. 5. positional tolerance applies to all three exposed pads in both x and y axis. dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.15 0.25 d 6.00 bsc d2 4.53 4.73 e 6.00 bsc 2.06 e2 1.86 e 0.40 bsc l 0.25 0.45 l1 ??? 0.15 note 3 plane dimensions: millimeters 0.25 4.81 0.40 2.09 48x 6.30 6.30 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* e/2 detail b l1 detail a l alternate terminal constructions l 1.45 bsc pitch detail c 45 d3 1.64 1.84 d4 2.42 2.62 2.61 e3 2.41 2.50 e4 2.30 g4 1.06 bsc h2 1.40 bsc h3 1.19 bsc l2 0.15 ref h4 1.10 bsc l2 d4 d3 e4 e2 48x a m 0.10 b c m m 1 13 25 48 bottom view detail c 37 h3 supplemental h2 h4 g3 g4 note 5 0.58 48x 2.54 4.80 2.66 1.91 recommended d5 d5 4.58 4.78
ncp81252 www. onsemi.com 18 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81252/d intel is a registered trademark of intel corporation in the u.s. and/or other countries. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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